Recent technological advances in the semiconductor industry permitted dramatic increases in integrated circuit density and complexity. These improvements have led to a dramatic increase in their use in a variety of applications, especially digital applications. An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (which results in a low price), with DRAM cell size being typically between 6 F2 and 8 F2 (where F is the minimum feature size). However, with typical DRAM access times of approximately 50 nsec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density, with typical cell size being between about 60 F2 and 150 F2.
Recently, a new type of memory cells has been developed. These cells consist of a NDR (Negative Differential Resistance) device having a control port that is capacitively coupled to a relatively thin thyristor body. The thyristor body is sufficiently thin to permit modulation of the potential of the thyristor body in response to selected signals capacitively coupled via the control port. Such capacitively-coupled signals are used to enhance switching of the thyristor-based device between current-blocking and current-conducting states. One advantage of this type of cells is that the cell size is much smaller than the four-transistor and six-transistor SRAM cells.
An important consideration in the design of thyristor-based memory cells, including the above described thyristor-based type, concerns maintenance of the thyristor's conducting state. When the thyristor is in the forward conducting state, a DC current larger than the holding current of the thyristor flows through the thyristor in order to maintain the conducting state. One method to maintain the conducting state is to use a restoration circuit to periodically apply a voltage or current pulse to the thyristor so that data in the cell is restored using the internal positive feedback loop of the thyristor. The pulse waveform and frequency are defined to ensure that the transistor is not released from its conducting state. This restoration is typically applied after the thyristor device is fully in the forward conducting state and in a manner that prevents the thyristor device from transitioning completely out of the forward conducting state. This method is described in a patent document WO 02/082451 A1 published Oct. 17, 2002 and entitled “Dynamic Data Restore in Thyristor-Based Memory Device.”